Two major types of random access memory cells—dynamic and static—are currently used in the semiconductor industry. Dynamic random-access memories (DRAM) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. Static random-access memory are so called because they do not require periodic refreshing.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components, a filed effect transistor (FET) and a capacitor.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 42. For each cell, the capacitor 44 has two connections, which are located on opposite sides of capacitor 44. The first connection is to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The second connection is to the drain of the FET 46. The gate of the FET 46 is connected to the word line 48, and the source of the FET is connected to the bit line 50. This connection enables the word line 48 to control access to the capacitor 44 by allowing or preventing a signal (a logical “0” or a logical “1”) on the bit line 50 to be written to or read from the capacitor 44.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and several contacts, including one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the capacitor, and the compatibility of array devices with non-array devices.
A drawback of conventional DRAM fabrication is the inability of the process to achieve a minimal space or minimal critical dimension (CD) between two adjacent word lines and, consequently, between two adjacent memory cells. To illustrate this drawback, reference is made to FIG. 2 which shows a top view of a conventional DRAM array layout 20 formed over a semiconductor substrate 10. Four word lines 48a, 48b, 48c and 48d intersect three bit lines 50 to define six field effect transistors 46a, 46b, 46c, 46d, 46e and 46f. The DRAM array layout 20 also illustrates four bit contacts 52 as well as six cell capacitor nodes 44 disposed adjacent to respective field effect transistors. The space between two adjacent word lines, for example between word lines 48b and 48c, is represented in FIG. 2 as dimension D. This space is typically required to optically separate the adjacent word lines during photolithography.
FIG. 3 illustrates a cross-sectional view of the conventional DRAM array layout 20, taken along line 3-3′, but at an earlier stage of processing. As shown in FIG. 3, the two adjacent word lines 48b and 48c are spaced apart at the distance D. Also shown formed on the semiconductor substrate 10 are a field oxide region 12 and source and drain regions 14b, 16b, 14e and 16e of the field effect transistors 46b and 46e (FIG. 2), respectively. With increasing packing density of DRAM cells, it is desirable for the distance D (FIGS. 2-3) to decrease to values below 500 Angstroms, and preferably to less than or equal to 300 Angstroms, or even less than 100 Angstroms, but current lithography technologies do not afford these values. The decrease in the distance D between the two adjacent word lines 48b and 48c would in turn confer more device area for the adjacent field effect transistors 46b and 46e, respectively, as well as for the cell capacitor nodes 44 adjacent to field effect transistors 46b and 46e. As known in the art, the cell capacitor nodes, for example, require maximum area to allow self-aligned etches and to achieve good contact resistance.
Conventional folded bit line cells of the 256 Mbit generation with planar devices have been created to a size of at least 8F2, where F is the minimum lithographic feature size. If a folded bit line is not used, the cell may be reduced to 6F2 or 4F2. Cell sizes of 4F2 may be achieved by using vertical transistors stacked either below or above the cell capacitors, to form, for example, the so-called “cross-cell points,” which have a memory cell located at the intersection of each bit line and each word line. However, these cells are expensive and difficult to fabricate because the structure of the array devices is typically incompatible with that of the non-array devices.
There is needed, therefore, an improved method for fabricating memory structures having word lines which are minimally spaced from each other, as well as a method for decreasing the distance between two adjacent word lines formed on an integrated circuit. There is also a need for decreasing the minimum lithographic feature size in a DRAM array and, consequently, the size of the DRAM cell, as well as a method for increasing the memory cell density.